Xiang Gao, Olivier Burg, Haisong Wang, Wanghua Wu, Cao-Thong Tu, Konstantinos Manetakis, Fan Zhang, Luns Tee, Mustafa Yayla, Sining Xiang, Randy Tsang, Li Lin. 9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS. In 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016. pages 174-175, IEEE, 2016. [doi]
Abstract is missing.