FPGA implementation of a challenge pre-processing structure arbiter PUF designed for machine learning attack resistance - researchr publication

researchr

You are not signed in
Sign in
Sign up

Wei Ge, Shenxin Hu, Ji-quan Huang, Bo Liu 0019, Min Zhu. FPGA implementation of a challenge pre-processing structure arbiter PUF designed for machine learning attack resistance. IEICE Electronic Express, 17(2):20190670, 2020. [doi]

Abstract is missing.

runs on WebDSL