UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog

Nikolaos Georgoulopoulos, Ioannis Giannou, Alkiviadis A. Hatzopoulos. UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog. In 28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2018, Platja d'Aro, Spain, July 2-4, 2018. pages 97-102, IEEE, 2018. [doi]

Abstract

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