Sequential logic synthesis for testability using register-transfer level descriptions

Abhijit Ghosh, Srinivas Devadas, A. Richard Newton. Sequential logic synthesis for testability using register-transfer level descriptions. In Proceedings IEEE International Test Conference 1990, Washington, D.C., USA, September 10-14, 1990. pages 274-283, IEEE Computer Society, 1990. [doi]

Abstract

Abstract is missing.