Hans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon. Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays. In Jonathan W. Greene, Jason Helge Anderson, editors, Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2017, Monterey, CA, USA, February 22-24, 2017. pages 85-94, ACM, 2017. [doi]
Abstract is missing.