Effective FPGA debug for high-level synthesis generated circuits

Jeffrey B. Goeders, Steven J. E. Wilton. Effective FPGA debug for high-level synthesis generated circuits. In 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014. pages 1-8, IEEE, 2014. [doi]

Abstract

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