FPGA latency optimization using system-level transformations and DFG restructuring

Daniel Gomez-Prado, Maciej J. Ciesielski, Russell Tessier. FPGA latency optimization using system-level transformations and DFG restructuring. In Enrico Macii, editor, Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013. pages 1553-1558, EDA Consortium San Jose, CA, USA / ACM DL, 2013. [doi]

Abstract

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