Design re-use for compile time reduction in FPGA high-level synthesis flows

Marcel Gort, Jason Helge Anderson. Design re-use for compile time reduction in FPGA high-level synthesis flows. In Jialin Chen, Wenbo Yin, Yuichiro Shibata, Lingli Wang, Hayden Kwok-Hay So, Yuchun Ma, editors, 2014 International Conference on Field-Programmable Technology, FPT 2014, Shanghai, China, December 10-12, 2014. pages 4-11, IEEE, 2014. [doi]

Abstract

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