PEFSL: A deployment Pipeline for Embedded Few-Shot Learning on a FPGA SoC

Lucas Grativol, Lubin Gauthier, Mathieu Léonardon, Jérémy Morlier, Antoine Lavrard-Meyer, Guillaume Muller 0001, Virginie Fresse, Matthieu Arzel. PEFSL: A deployment Pipeline for Embedded Few-Shot Learning on a FPGA SoC. In IEEE International Symposium on Circuits and Systems, ISCAS 2024, Singapore, May 19-22, 2024. pages 1-5, IEEE, 2024. [doi]

Abstract

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