Influence of different layout styles on the performance of the calibration of an on-chip programmable voltage reference

Dominik Gruber, Timm Ostermann. Influence of different layout styles on the performance of the calibration of an on-chip programmable voltage reference. In Erik Brunvard, Ken Stevens, Joseph R. Cavallaro, Tong Zhang 0002, editors, Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake Cit, UT, USA, May 3-4, 2012. pages 195-200, ACM, 2012. [doi]