Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction

Fazal Hameed, Lars Bauer, Jörg Henkel. Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems, 35(4):651-664, 2016. [doi]

Abstract

Abstract is missing.