A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement

Fazal Hameed, Jerónimo Castrillón. A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement. IEEE Trans. VLSI Syst., 27(10):2375-2386, 2019. [doi]

Abstract

Abstract is missing.