A VLSI architecture for high-performance, low-cost, on-chip learning

Dan W. Hammerstrom. A VLSI architecture for high-performance, low-cost, on-chip learning. In IJCNN 1990, International Joint Conference on Neural Networks, San Diego, CA, USA, June 17-21, 1990. pages 537-544, IEEE, 1990. [doi]

Abstract

Abstract is missing.