Design of Error-Resilient Logic Gates with Reinforcement Using Implications

Xijing Han, Marco Donato, R. Iris Bahar, Alexander Zaslavsky, William R. Patterson. Design of Error-Resilient Logic Gates with Reinforcement Using Implications. In Ayse Kivilcim Coskun, Martin Margala, Laleh Behjat, Jie Han, editors, Proceedings of the 26th edition on Great Lakes Symposium on VLSI, GLVLSI 2016, Boston, MA, USA, May 18-20, 2016. pages 191-196, ACM, 2016. [doi]

@inproceedings{HanDBZP16,
  title = {Design of Error-Resilient Logic Gates with Reinforcement Using Implications},
  author = {Xijing Han and Marco Donato and R. Iris Bahar and Alexander Zaslavsky and William R. Patterson},
  year = {2016},
  doi = {10.1145/2902961.2902983},
  url = {http://doi.acm.org/10.1145/2902961.2902983},
  researchr = {https://researchr.org/publication/HanDBZP16},
  cites = {0},
  citedby = {0},
  pages = {191-196},
  booktitle = {Proceedings of the 26th edition on Great Lakes Symposium on VLSI, GLVLSI  2016, Boston, MA, USA, May 18-20, 2016},
  editor = {Ayse Kivilcim Coskun and Martin Margala and Laleh Behjat and Jie Han},
  publisher = {ACM},
  isbn = {978-1-4503-4274-2},
}