Design of Error-Resilient Logic Gates with Reinforcement Using Implications

Xijing Han, Marco Donato, R. Iris Bahar, Alexander Zaslavsky, William R. Patterson. Design of Error-Resilient Logic Gates with Reinforcement Using Implications. In Ayse Kivilcim Coskun, Martin Margala, Laleh Behjat, Jie Han, editors, Proceedings of the 26th edition on Great Lakes Symposium on VLSI, GLVLSI 2016, Boston, MA, USA, May 18-20, 2016. pages 191-196, ACM, 2016. [doi]