Automatic Verification of Mixed-Level Logic Circuits

F. Keith Hanna. Automatic Verification of Mixed-Level Logic Circuits. In Ganesh Gopalakrishnan, Phillip J. Windley, editors, Formal Methods in Computer-Aided Design, Second International Conference, FMCAD 98, Palo Alto, California, USA, November 4-6, 1998, Proceedings. Volume 1522 of Lecture Notes in Computer Science, pages 133-166, Springer, 1998. [doi]

Abstract

Abstract is missing.