Naoaki Harada, Naoyuki Matsumoto, Koji Nakano, Yasuaki Ito. A Hardware Sorter for Almost Sorted Sequences, with FPGA Implementations. In Fourth International Symposium on Computing and Networking, CANDAR 2016, Hiroshima, Japan, November 22-25, 2016. pages 565-571, IEEE, 2016. [doi]
Abstract is missing.