An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors

Tetsutaro Hashimoto, Yukihito Kawabe, Michiharu Hara, Yasushi Kakimura, Kunihiko Tajiri, Shinichiro Shirota, Ryuichi Nishiyama, Hitoshi Sakurai, Hiroshi Okano, Yasumoto Tomita, Sugio Satoh, Hideo Yamashita. An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors. J. Solid-State Circuits, 53(4):1028-1037, 2018. [doi]

Abstract

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