Analysis of triggering behaviour of high voltage CMOS LDMOS clamps and SCRs during ESD induced latch-up

M. Heer, V. Dubec, Scrgey Bychikhin, Dionyz Pogany, E. Gornik, M. Frank, A. Konrad, J. Schulz. Analysis of triggering behaviour of high voltage CMOS LDMOS clamps and SCRs during ESD induced latch-up. Microelectronics Reliability, 46(9-11):1591-1596, 2006. [doi]

Abstract

Abstract is missing.