Power Reducing Techniques for Clocked CMOS PLAs

Richard F. Hobson. Power Reducing Techniques for Clocked CMOS PLAs. In 8th Great Lakes Symposium on VLSI (GLS-VLSI 98), 19-21 February 1998, Lafayette, LA, USA. pages 34-38, IEEE Computer Society, 1998. [doi]

Abstract

Abstract is missing.