A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard

Liang Hong, Weifeng He, Hui Zhu, Zhigang Mao. A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard. IEICE Electronic Express, 10(9):20130210, 2013. [doi]

Abstract

Abstract is missing.