A 145µW 8×8 parallel multiplier based on optimized bypassing architecture

Sunjoo Hong, Taehwan Roh, Hoi-Jun Yoo. A 145µW 8×8 parallel multiplier based on optimized bypassing architecture. In International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil. pages 1175-1178, IEEE, 2011. [doi]

Abstract

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