A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits - researchr publication

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Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka. A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits. In 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It s a Gamble, 28 April - 2 May 2002, Monterey, CA, USA. pages 328-335, IEEE Computer Society, 2002. [doi]

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