Tunneling transistor based 6T SRAM bitcell circuit design in sub-10nm domain

Nahid M. Hossain, Arif Iqbal, Hemanshu Shishupal, Masud H. Chowdhury. Tunneling transistor based 6T SRAM bitcell circuit design in sub-10nm domain. In IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017. pages 1485-1488, IEEE, 2017. [doi]

Abstract

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