A low-voltage sinc/sup 2/ decimator implemented by a new circuit technique using floating-gate MOS transistors

Mats Høvin, Dag T. Wisland, Yngvar Berg, Tor Sverre Lande. A low-voltage sinc/sup 2/ decimator implemented by a new circuit technique using floating-gate MOS transistors. In ISCAS (4). pages 397-400, 2002. [doi]

Abstract

Abstract is missing.