SDRAM Delay Fault Modeling and Performance Testing

Yu-Tsao Hsing, Chun-Chieh Huang, Jen-Chieh Yeh, Cheng-Wen Wu. SDRAM Delay Fault Modeling and Performance Testing. In 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA. pages 53-58, IEEE Computer Society, 2007. [doi]

Authors

Yu-Tsao Hsing

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Chun-Chieh Huang

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Jen-Chieh Yeh

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Cheng-Wen Wu

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