Chengyu Hu, Qinghua Duan, Peng Lu, Wei Liu, Jian Wang, Jinmei Lai. A Tile-based Interconnect Model for FPGA Architecture Exploration. In Tinoosh Mohsenin, Weisheng Zhao, Yiran Chen, Onur Mutlu, editors, GLSVLSI '20: Great Lakes Symposium on VLSI 2020, Virtual Event, China, September 7-9, 2020. pages 113-118, ACM, 2020. [doi]
Abstract is missing.