6-T SRAM performance assessment with stacked silicon nanowire MOSFETs

Ya-Chi Huang, Meng-Hsueh Chiang, Wei-Chou Hsu, Shiou-Ying Cheng. 6-T SRAM performance assessment with stacked silicon nanowire MOSFETs. In Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015. pages 610-614, IEEE, 2015. [doi]

Abstract

Abstract is missing.