Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications

Ya-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang. Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications. In 20th International Symposium on Quality Electronic Design, ISQED 2019, Santa Clara, CA, USA, March 6-7, 2019. pages 231-234, IEEE, 2019. [doi]

@inproceedings{HuangCW19-1,
  title = {Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications},
  author = {Ya-Chi Huang and Meng-Hsueh Chiang and Shui-Jinn Wang},
  year = {2019},
  doi = {10.1109/ISQED.2019.8697706},
  url = {https://doi.org/10.1109/ISQED.2019.8697706},
  researchr = {https://researchr.org/publication/HuangCW19-1},
  cites = {0},
  citedby = {0},
  pages = {231-234},
  booktitle = {20th International Symposium on Quality Electronic Design, ISQED 2019, Santa Clara, CA, USA, March 6-7, 2019},
  publisher = {IEEE},
  isbn = {978-1-7281-0392-1},
}