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Cross-layer optimized placement and routing for FPGA soft error mitigation

Keheng Huang, Yu Hu, Xiaowei Li 0001. Cross-layer optimized placement and routing for FPGA soft error mitigation. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011. pages 58-63, IEEE, 2011. [doi]

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