Safeen Huda, Muntasir Mallick, Jason Helge Anderson. Clock gating architectures for FPGA power reduction. In Martin Danek, Jiri Kadlec, Brent E. Nelson, editors, 19th International Conference on Field Programmable Logic and Applications, FPL 2009, August 31 - September 2, 2009, Prague, Czech Republic. pages 112-118, IEEE, 2009. [doi]
@inproceedings{HudaMA09,
title = {Clock gating architectures for FPGA power reduction},
author = {Safeen Huda and Muntasir Mallick and Jason Helge Anderson},
year = {2009},
doi = {10.1109/FPL.2009.5272538},
url = {http://dx.doi.org/10.1109/FPL.2009.5272538},
tags = {architecture},
researchr = {https://researchr.org/publication/HudaMA09},
cites = {0},
citedby = {0},
pages = {112-118},
booktitle = {19th International Conference on Field Programmable Logic and Applications, FPL 2009, August 31 - September 2, 2009, Prague, Czech Republic},
editor = {Martin Danek and Jiri Kadlec and Brent E. Nelson},
publisher = {IEEE},
isbn = {978-1-4244-3892-1},
}