Abstract is missing.
- Register Queues: A New Hardware/Software Approach to Efficient Software PipeliningMikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson. 3-12 [doi]
- Region Formation Analysis with Demand-Driven Inlining for Region-Based OptimizationTom Way, Ben Breech, Lori L. Pollock. 24-36 [doi]
- aSOC: A Scalable, Single-Chip Communications ArchitectureJian Liang, Sriram Swaminathan, Russell Tessier. 37-46 [doi]
- Address Partitioning in DSM Clusters with Parallel Coherence ControllersIlanthiraiyan Pragaspathy, Babak Falsafi. 47-56 [doi]
- Custom Wide Counterflow Pipelines for High-Performance Embedded ApplicationsBruce R. Childers, Jack W. Davidson. 57-70 [doi]
- A Lightweight Algorithm for Dynamic If-Conversion during Dynamic OptimizationKim M. Hazelwood, Thomas M. Conte. 71-80 [doi]
- Exploring the Limits of Sub-Word Level ParallelismKevin Scott, Jack W. Davidson. 81-91 [doi]
- The Dynamic Trace Memorization Reuse TechniqueAmarildo T. da Costa, Felipe M. G. França, Eliseu M. Chaves Filho. 92-99 [doi]
- Exploring Sub-Block Value Reuse for Superscalar ProcessorsJian Huang, David J. Lilja. 100-110 [doi]
- Hiding Relaxed Memory Consistency with CompilersJaejin Lee, David A. Padua. 111-122 [doi]
- Neighborhood Prefetching on Multiprocessors Using Instruction HistoryDavid M. Koppelman. 123-132 [doi]
- Characterization of Silent StoresGordon B. Bell, Kevin M. Lepak, Mikko H. Lipasti. 133-144 [doi]
- On Some Implementation Issues for Value Prediction on Wide-Issue ILP ProcessorsSang-Jeong Lee, Pen-Chung Yew. 145-156 [doi]
- A Unified Compiler Framework for Control and Data SpeculationRoy Dz-Ching Ju, Kevin Nomura, Uma Mahadevan, Le-Chun Wu. 157-168 [doi]
- Applying Data Speculation in Modulo Scheduled LoopsUma Mahadevan, Kevin Nomura, Roy Dz-Ching Ju, Rick Hank. 169-178 [doi]
- Branch Prediction in Multi-Threaded ProcessorsJayanth Gummaraju, Manoj Franklin. 179-188 [doi]
- The Effect of Code Reordering on Branch PredictionAlex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero. 189-198 [doi]
- A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to Wrong-History MispredictionsKevin Skadron, Margaret Martonosi, Douglas W. Clark. 199-206 [doi]
- Dynamic Branch Prediction for a VLIW ProcessorJan Hoogerbrugge. 207-216 [doi]
- Fine Grained Multithreading with Process CalculiLuís M. B. Lopes, Fernando M. A. Silva, Vasco Thudichum Vasconcelos. 217-226 [doi]
- Data Relation Vectors: A New Abstraction for Data OptimizationsMahmut T. Kandemir, J. Ramanujam. 227-236 [doi]
- Combined Selection of Tile Sizes and Unroll Factors Using Iterative CompilationToru Kisuki, Peter M. W. Knijnenburg, Michael F. P. O Boyle. 237-248 [doi]
- Faster FFTs via Architecture-CognizanceKang Su Gatlin, Larry Carter. 249-260 [doi]
- Hybrid Parallel Circuit Simulation ApproachesEdwin Naroska, Rung-Ji Shang, Feipei Lai, Uwe Schwiegelshohn. 261-270 [doi]
- Multithreaded Programming of PC ClustersMartin Schulz. 271-280 [doi]
- A Fast Algorithm for Scheduling Instructions with Deadline Constraints on RISC ProcessorsHui Wu, Joxan Jaffar, Roland H. C. Yap. 281-290 [doi]
- Instruction Scheduling for Clustered VLIW DSPsRainer Leupers. 291-300 [doi]
- Efficient Backtracking Instruction SchedulersSantosh G. Abraham, Waleed Meleis, Ivan D. Baev. 301-308 [doi]