A 600-MHz 54/spl times/54-bit multiplier with rectangular-styled Wallace tree

Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba. A 600-MHz 54/spl times/54-bit multiplier with rectangular-styled Wallace tree. J. Solid-State Circuits, 36(2):249-257, 2001. [doi]

Authors

Niichi Itoh

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Yuka Naemura

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Hiroshi Makino

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Yasunobu Nakase

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Tsutomu Yoshihara

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Yasutaka Horiba

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