A 600-MHz 54/spl times/54-bit multiplier with rectangular-styled Wallace tree

Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba. A 600-MHz 54/spl times/54-bit multiplier with rectangular-styled Wallace tree. J. Solid-State Circuits, 36(2):249-257, 2001. [doi]

@article{ItohNMNYH01,
  title = {A 600-MHz 54/spl times/54-bit multiplier with rectangular-styled Wallace tree},
  author = {Niichi Itoh and Yuka Naemura and Hiroshi Makino and Yasunobu Nakase and Tsutomu Yoshihara and Yasutaka Horiba},
  year = {2001},
  doi = {10.1109/4.902765},
  url = {https://doi.org/10.1109/4.902765},
  researchr = {https://researchr.org/publication/ItohNMNYH01},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {36},
  number = {2},
  pages = {249-257},
}