Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support

Manish Kumar Jaiswal, Ray C. C. Cheung. Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support. Microelectronics Journal, 44(5):421-430, 2013. [doi]

Abstract

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