High Performance, Low Latency Double Digit Decimal Multiplier on ASIC and FPGA - researchr publication

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Rekha K. James, K. Poulose Jacob, Sreela Sasi. High Performance, Low Latency Double Digit Decimal Multiplier on ASIC and FPGA. In World Congress on Nature & Biologically Inspired Computing, NaBIC 2009, 9-11 December 2009, Coimbatore, India. pages 1445-1450, IEEE, 2009. [doi]

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