Low-Power 32bit×32bit Multiplier Design with Pipelined Block-Wise Shutdown

Yong-Ju Jang, Yoan Shin, Min-Cheol Hong, Jae-Kyung Wee, Seongsoo Lee. Low-Power 32bit×32bit Multiplier Design with Pipelined Block-Wise Shutdown. In David A. Bader, Manish Parashar, Sridhar Varadarajan, Viktor K. Prasanna, editors, High Performance Computing - HiPC 2005, 12th International Conference, Goa, India, December 18-21, 2005, Proceedings. Volume 3769 of Lecture Notes in Computer Science, pages 398-406, Springer, 2005. [doi]

Abstract

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