A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract)

David Jefferson, Srinivas Reddy, Christopher Lane, Ninh Ngo, Wanli Chang, Manuel Mijia, Ketan Zaveri, Cameron McClintock, Richard Cliff. A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract). In FPGA. pages 256, 1998. [doi]

@inproceedings{JeffersonRLNCMZMC98,
  title = {A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract)},
  author = {David Jefferson and Srinivas Reddy and Christopher Lane and Ninh Ngo and Wanli Chang and Manuel Mijia and Ketan Zaveri and Cameron McClintock and Richard Cliff},
  year = {1998},
  doi = {10.1145/275107.275148},
  url = {http://doi.acm.org/10.1145/275107.275148},
  tags = {logic programming, logic},
  researchr = {https://researchr.org/publication/JeffersonRLNCMZMC98},
  cites = {0},
  citedby = {0},
  pages = {256},
  booktitle = {FPGA},
}