FPGA acceleration of Sparse Matrix-Vector Multiplication based on Network-on-Chip - researchr publication

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Hong-Yuan Jheng, C. C. Sun, S.-J. Ruan, Jürgen Götze. FPGA acceleration of Sparse Matrix-Vector Multiplication based on Network-on-Chip. In Proceedings of the 19th European Signal Processing Conference, EUSIPCO 2011, Barcelona, Spain, August 29 - Sept. 2, 2011. pages 744-748, IEEE, 2011. [doi]

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