An efficient RISC-V processor with customized instruction set for sparse DNN acceleration on embedded system - researchr publication

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Bowen Jiang, Jianyang Ding, Huachen Zhang, Tianshuo Lu, ZhiLei Chai. An efficient RISC-V processor with customized instruction set for sparse DNN acceleration on embedded system. Journal of Systems Architecture, 171:103649, 2026. [doi]

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