Fradaric Joseph, Kiran Francis, Archita Hore, Siddhanta Roy, S. Josephine, Roy P. Paily. An efficient hardware architecture for stereo disparity estimation. In 18th International Symposium on VLSI Design and Test, VDAT 2014, Coimbatore, India, July 16-18, 2014. pages 1-6, IEEE, 2014. [doi]
Abstract is missing.