A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits

Smriti Joshi, Anne Lombardot, Marc Belleville, Edith Beigné, Stéphane Girard. A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits. In Enrico Macii, editor, Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013. pages 1056-1057, EDA Consortium San Jose, CA, USA / ACM DL, 2013. [doi]

Abstract

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