A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations

Akira Katsuno, Hiromasa Takahashi, Hajime Kubosawa, Tomio Sato, Atsuhiro Suga, Gensuke Goto. A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations. In Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1990, Cambridge, MA, USA, 17-19 September, 1990. pages 347-350, IEEE, 1990. [doi]

Abstract

Abstract is missing.