3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS

Takashi Kawamoto, Takayasu Norimatsu, Kenji Kogo, Fumio Yuki, Norio Nakajima, Masatoshi Tsuge, Tatsunori Usugi, Tomofumi Hokari, Hideki Koba, Takemasa Komori, Junya Nasu, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, Jun Kumazawa, Hiroaki Kurahashi, Takashi Muto, Takeo Yamashita, Masatoshi Hasegawa, Keiichi Higeta. 3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS. In 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015. pages 1-3, IEEE, 2015. [doi]

@inproceedings{KawamotoNKYNTUH15,
  title = {3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS},
  author = {Takashi Kawamoto and Takayasu Norimatsu and Kenji Kogo and Fumio Yuki and Norio Nakajima and Masatoshi Tsuge and Tatsunori Usugi and Tomofumi Hokari and Hideki Koba and Takemasa Komori and Junya Nasu and Tsuneo Kawamata and Yuichi Ito and Seiichi Umai and Jun Kumazawa and Hiroaki Kurahashi and Takashi Muto and Takeo Yamashita and Masatoshi Hasegawa and Keiichi Higeta},
  year = {2015},
  doi = {10.1109/ISSCC.2015.7062922},
  url = {http://dx.doi.org/10.1109/ISSCC.2015.7062922},
  researchr = {https://researchr.org/publication/KawamotoNKYNTUH15},
  cites = {0},
  citedby = {0},
  pages = {1-3},
  booktitle = {2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015},
  publisher = {IEEE},
  isbn = {978-1-4799-6224-2},
}