Tak-Yung Kim, Taewhan Kim. Clock tree synthesis with pre-bond testability for 3D stacked IC designs. In Sachin S. Sapatnekar, editor, Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010. pages 723-728, ACM, 2010. [doi]
Abstract is missing.