A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

Young-Ju Kim 0001, Hye-Jung Kwon, Su-Yeon Doo, Min-Su Ahn, Yong Hun Kim, Yong Jae Lee, Dong-Seok Kang, Sung-Geun Do, Chang-Yong Lee, Gun-hee Cho, Jae-Koo Park, Jae-Sung Kim, Kyung Bae Park, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Hyun Soo Park, Jeong-Woo Lee, Seung Hyun Cho, Keon-Woo Park, Yong-Jun Kim, Young Hun Seo, Chang-Ho Shin, Chanyong Lee, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byung-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-jun Kwon, Jung Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin. A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking. J. Solid-State Circuits, 54(1):197-209, 2019. [doi]

Possibly Related Publications

The following publications are possibly variants of this publication: