Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction

Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa. Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction. In 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany. pages 646-647, IEEE Computer Society, 2005. [doi]

@inproceedings{KitaharaKMSF05,
  title = {Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction},
  author = {Takeshi Kitahara and Naoyuki Kawabe and Fumihiro Minami and Katsuhiro Seta and Toshiyuki Furusawa},
  year = {2005},
  doi = {10.1109/DATE.2005.68},
  url = {http://doi.ieeecomputersociety.org/10.1109/DATE.2005.68},
  tags = {design},
  researchr = {https://researchr.org/publication/KitaharaKMSF05},
  cites = {0},
  citedby = {0},
  pages = {646-647},
  booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March  2005, Munich, Germany},
  publisher = {IEEE Computer Society},
  isbn = {0-7695-2288-2},
}