Debugging VHDL Designs Using Temporal Process Instances

Daniel Köb, Bernhard Peischl, Franz Wotawa. Debugging VHDL Designs Using Temporal Process Instances. In Paul W. H. Chung, Chris J. Hinde, Moonis Ali, editors, Developments in Applied Artificial Intelligence, 16th International Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems, IEA/AIE 2003, Laughborough, UK, June 23-26, 2003, Proceedings. Volume 2718 of Lecture Notes in Computer Science, pages 402-415, Springer, 2003. [doi]

Abstract

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