Processor with 4.9-μs break-even time in power gating using crystalline In-Ga-Zn-oxide transistor

Hidetomo Kobayashi, Kiyoshi Kato, Takuro Ohmaru, Seiichi Yoneda, Tatsuji Nishijima, Shuhei Maeda, Kazuaki Ohshima, Hikaru Tamura, Hiroyuki Tomatsu, Tomoaki Atsumi, Yutaka Shionoiri, Yukio Maehashi, Jun Koyama, Shunpei Yamazaki. Processor with 4.9-μs break-even time in power gating using crystalline In-Ga-Zn-oxide transistor. In 2013 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVI, Yokohama, Japan, April 17-19, 2013. pages 1-3, IEEE, 2013. [doi]

Authors

Hidetomo Kobayashi

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Kiyoshi Kato

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Takuro Ohmaru

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Seiichi Yoneda

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Tatsuji Nishijima

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Shuhei Maeda

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Kazuaki Ohshima

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Hikaru Tamura

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Hiroyuki Tomatsu

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Tomoaki Atsumi

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Yutaka Shionoiri

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Yukio Maehashi

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Jun Koyama

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Shunpei Yamazaki

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