Circuit-Size Reduction for Parallel Chien Search using Minimal Polynomial Degree Reduction

Naoaki Kokubun, Akira Yamaga, Hironori Uchikawa, Daiki Watanabe. Circuit-Size Reduction for Parallel Chien Search using Minimal Polynomial Degree Reduction. In IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019. pages 1-5, IEEE, 2019. [doi]

Abstract

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